Serial Peripheral Interface LPC21xx - ARM7 Tutorials
- Posted by admin
- on Jan, 29, 2013
- in ARM Microcontroller, ARM7, Electronics, Interfacing Tutorial, LPC21xx, NXP
- Blog No Comments.
Reference : Document UM10139 Chapter 12
Purpose:
To learn, How to enable & use the inbuilt SPI module of LPC21xx, related Registers & idea of SPI bus ???
Objective is to perform an experiment in which, 8 LEDs are connected to SPI0 bus of LPC2148 using 74HC595 serial to parallel shift register. We need to display the 8 bit data sent over SPI0 bus onto the 8 LEDs. (Hardware connections are given)
Idea of SPI:

image source - Atmel AVR Primer: Programming & Interfacing, by Steven F. Barrett & Daniel J. Pack
SPI communication is based on MASTER, SLAVE concept. One of the communicating device is master and other is slave. SPI can be viewed as an Synchronous 16 bit[1] shift register with an 8 bit half residing in the Master side and other 8 bit half residing in the Slave side. Simply speaking it makes a common 16 bit circular buffer shared between master and slave. The basic concept is that, when master pulse out a bit of data, immediately it comes in the shift register of slave. everything is synchronized with the master clock generated by Master device.
Master can select one of many slaves by pulling Slave Select pin of that particular device LOW. When slave’s pin is made low by Master, slave’s shifting capability is enabled.
Master pulse out data bits on MOSI (Master Out Slave In) line, Slave pulse out data bits on MISO (Master In Slave Out) synchronized with the clock generated by Master.After eight master clock pulses on SCK line, a byte of data has been exchanged between master and slave designated SPI devices. Completion of data transmission by Master and reception by slave is signaled by setting of SPIF flag by SPI module. SPIF flag bit is located as the 7th bit (MSB) of SPSR (SPI status register).
Code Snippet
[1] - In case of LPC2148, we can change the number of data bits transferred at once by setting BitEnable(2nd) bit in SPI control register as HIGH.
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